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Architecture Decision Records documenting the Frontier Plan: - ADR-001: Ruvector Core Architecture - 6-layer architecture (Application → Storage) - SIMD intrinsics (AVX2/NEON) with 61us p50 latency - HNSW indexing with 16,400 QPS throughput - Integration points: Policy Memory, Session Index, Witness Log - ADR-002: RuvLLM Integration Architecture - Paged attention mechanism (mistral.rs-inspired) - Three Ruvector integration roles - SONA self-learning integration - Complete data flow architecture - ADR-003: SIMD Optimization Strategy - NEON implementation for Apple Silicon - AVX2/AVX-512 for x86_64 - Benchmark results: 2.96x-5.96x speedups - ADR-004: KV Cache Management - Three-tier adaptive cache (Hot/Warm/Archive) - KIVI, SQuat, KVQuant quantization strategies - 8-22x compression with <0.3 PPL degradation - ADR-005: WASM Runtime Integration - Wasmtime for servers, WAMR for embedded - Epoch-based interruption (2-5% overhead) - Kernel pack security with Ed25519 signatures - ADR-006: Memory Management & Unified Paging - 2MB page unified arena - S-LoRA style multi-tenant adapter serving - LRU eviction with hysteresis Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com> |
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| .. | ||
| ADR-001-ruvector-core-architecture.md | ||
| ADR-002-ruvllm-integration.md | ||
| ADR-003-simd-optimization-strategy.md | ||
| ADR-004-kv-cache-management.md | ||
| ADR-005-wasm-runtime-integration.md | ||
| ADR-006-memory-management.md | ||