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docs: Add AD-20 SIMD-only training mode for Phase 0.5 in ADR/DDD
Analyze RLM training stack GPU dependencies and document that Phase 0.5 runs entirely on pure CPU SIMD (NEON on aarch64) without Metal GPU. MicroLoRA, TrainingPipeline, EwcRegularizer, GrpoOptimizer are all pure ndarray; ContrastiveTrainer has explicit CPU fallback. Only ~2-3x slower than Metal. Extends platform support to Linux ARM64 and x86 (scalar). https://claude.ai/code/session_011nTcGcn49b8YKJRVoh4TaK
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2 changed files with 161 additions and 20 deletions
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@ -384,8 +384,8 @@ Keep GLM-4.7-Flash structure but replace only the expert MLP layers with BitLine
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### Phase 0.5: RLM Post-Quantization Refinement (NEW — Mac Studio, $0)
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- **Timeline**: 1-3 weeks (overlaps with Phase 0 kernel development)
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- **Cost**: **$0** (runs on Mac Studio, ~2-12 days training wall time)
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- **Platform**: Mac Studio (same as Phase 0)
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- **Cost**: **$0** (runs on Mac Studio, ~2-12 days training wall time with Metal; ~4-24 days SIMD-only)
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- **Platform**: Mac Studio (same as Phase 0) — **supports both Metal GPU and pure SIMD/CPU modes** (see AD-20)
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- **Goal**: Improve Phase 0 PTQ quality from ~55-65% to ~70-80% by training only the small FP16 components using the existing RLM stack — **no traditional distillation, no cloud GPU**
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- **Approach**: Freeze ternary weights, train FP16 corrections using RLM components:
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1. **MicroLoRA adapters** (rank 1-2) on each expert FFN — adds small FP16 correction: `Y = BitLinear(X) + LoRA_B @ LoRA_A @ X`
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@ -396,7 +396,7 @@ Keep GLM-4.7-Flash structure but replace only the expert MLP layers with BitLine
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6. **Policy persistence** via PolicyStore — stores optimized per-layer configurations
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- **Trainable parameters**: ~200-400M (1-2% of 30B total) — router (~30M), MicroLoRA adapters (~50-100M), LM head (~150M), scale factors (~0.1M)
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- **Training data**: 100M-500M tokens (sufficient for <400M trainable params)
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- **Throughput**: ~500-1000 tok/s (Metal) × 100M-500M tokens = **2-12 days on Mac Studio**
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- **Throughput**: ~500-1000 tok/s (Metal) or ~200-500 tok/s (NEON SIMD only) × 100M-500M tokens = **2-12 days (Metal) or 4-24 days (SIMD-only) on Mac Studio**
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- **Deliverables**:
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- RLM-refined GGUF with ternary experts + optimized FP16 components
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- MicroLoRA adapter weights (exportable, ~20-100 MB)
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@ -853,16 +853,18 @@ let expert_results: Vec<DistillResult> = experts
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**Throughput and cost comparison:**
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| Platform | Training tok/s | Time (200B tok, Phase 1) | Cost | Phase 0 PTQ? |
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|----------|---------------|--------------------------|------|-------------|
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| **Mac Studio M4 Max (Metal)** | ~500-1000 | ~6.5 years | N/A | **Yes — 1-4 hrs, $0** |
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| **Mac Studio M3 Ultra (Metal)** | ~800-1500 | ~4.2 years | N/A | **Yes — 1-1.5 hrs, $0** |
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| CPU AVX2 (Ryzen 9) | ~50-100 | ~65 years | N/A | Yes — 2-6 hrs, $0 |
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| 1× A100 80GB (GCP on-demand) | ~15,000 | ~155 days | ~$3,700 | Yes — 30 min, ~$5 |
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| 4× A100 80GB (GCP on-demand) | ~50,000 | ~46 days | ~$4,400 | Overkill for PTQ |
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| 4× A100 80GB (GCP spot) | ~50,000 | ~46 days | **~$1,300** | Overkill for PTQ |
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| 1× H100 (DataCrunch) | ~40,000 | ~58 days | ~$2,900 | Overkill for PTQ |
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| 4× H100 (DataCrunch) | ~140,000 | ~16 days | **~$3,200** | Overkill for PTQ |
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| Platform | Training tok/s | Time (200B tok, Phase 1) | Cost | Phase 0 PTQ? | Phase 0.5 RLM? |
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|----------|---------------|--------------------------|------|-------------|---------------|
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| **Mac Studio M4 Max (Metal)** | ~500-1000 | ~6.5 years | N/A | **Yes — 1-4 hrs, $0** | **Yes — 2-12 days, $0** |
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| **Mac Studio M4 Max (NEON SIMD only, no Metal)** | ~200-500 | ~13 years | N/A | **Yes — 2-6 hrs, $0** | **Yes — 4-24 days, $0** |
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| **Mac Studio M3 Ultra (Metal)** | ~800-1500 | ~4.2 years | N/A | **Yes — 1-1.5 hrs, $0** | **Yes — 1.5-8 days, $0** |
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| **Mac Studio M3 Ultra (NEON SIMD only, no Metal)** | ~300-700 | ~9 years | N/A | **Yes — 1.5-3 hrs, $0** | **Yes — 3-16 days, $0** |
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| CPU AVX2 (Ryzen 9) — scalar fallback | ~50-150 | ~43-130 years | N/A | Yes — 2-6 hrs, $0 | Yes — 14-58 days, $0 |
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| 1× A100 80GB (GCP on-demand) | ~15,000 | ~155 days | ~$3,700 | Yes — 30 min, ~$5 | Overkill |
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| 4× A100 80GB (GCP on-demand) | ~50,000 | ~46 days | ~$4,400 | Overkill for PTQ | Overkill |
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| 4× A100 80GB (GCP spot) | ~50,000 | ~46 days | **~$1,300** | Overkill for PTQ | Overkill |
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| 1× H100 (DataCrunch) | ~40,000 | ~58 days | ~$2,900 | Overkill for PTQ | Overkill |
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| 4× H100 (DataCrunch) | ~140,000 | ~16 days | **~$3,200** | Overkill for PTQ | Overkill |
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**Key insight**: Mac Studio is infeasible for Phase 1+ training (years of wall time) but **ideal for Phase 0 PTQ** (hours, $0). This separation justifies the phased approach.
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@ -872,7 +874,8 @@ let expert_results: Vec<DistillResult> = experts
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|-------|----------|----------|----------------|----------|
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| **Phase 0 (PTQ)** | **Mac Studio (M4 Max/M3 Ultra)** | **1-4 hours** | **$0** | **Mmap FP16 weights → absmean quantize → export GGUF; Metal GPU for calibration pass** |
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| Phase 0D (BitDistill Lite, 10B tok) | Mac Studio Metal or 1× A100 spot | 2-4 weeks (local) / 1-2 days (cloud) | $0 (local) / ~$300 (cloud) | Optional quality upgrade if Phase 0C too degraded |
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| **Phase 0.5 (RLM refinement, 100-500M tok)** | **Mac Studio (Metal)** | **3-14 days** | **$0** | **MicroLoRA + router fix + scale opt using existing RLM stack** |
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| **Phase 0.5 (RLM refinement, Metal)** | **Mac Studio (Metal)** | **3-14 days** | **$0** | **MicroLoRA + router fix + scale opt using existing RLM stack** |
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| **Phase 0.5 (RLM refinement, SIMD-only)** | **Mac Studio (NEON CPU)** | **5-28 days** | **$0** | **Same pipeline, no Metal required — pure ndarray + NEON SIMD (see AD-20)** |
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| Phase 1 (expert FFN, 200B tok) | 4× A100 80GB spot (GCP) | ~46 days | $1,300-$2,000 | Per-expert sequential with EWC++; each expert fits 1 GPU |
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| Phase 1 (router validation) | Mac Studio Metal or 1× A100 | ~2-4 hours | $0 (local) / <$10 (cloud) | Contrastive training on router only (~2B params) |
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| Phase 2 (full ternary, 500B tok) | 4× H100 (DataCrunch) | ~16-32 days | $2,500-$5,000 | All layers; model-parallel across GPUs |
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@ -1155,6 +1158,100 @@ All three can be addressed by training only the FP16 components using the existi
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**Reused (100%)**: `MicroLoRA`, `TrainingPipeline`, `EwcRegularizer`, `GrpoOptimizer`, `ContrastiveTrainer`, `MemoryDistiller`, `PolicyStore`, `TrainingConfig`, LR schedules, GGUF export.
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**New (0%)**: No new training code. The only new code is a thin `RlmRefiner` orchestrator (~200-300 lines) that wires the existing components together for the Phase 0.5 pipeline.
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### AD-20: Phase 0.5 — SIMD-Only Training Mode (No Metal GPU Required)
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**Decision**: Phase 0.5 RLM refinement supports a pure SIMD/CPU execution mode with no Metal GPU dependency. Metal is an optional acceleration path (~2-3x faster) but not required.
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**Rationale**: Analysis of the RLM training stack reveals that Metal GPU is used by only one component (`RealContrastiveTrainer` via Candle), while all other training components are pure ndarray/CPU. Since Phase 0.5 uses the lightweight `ContrastiveTrainer` (not `RealContrastiveTrainer`) for router repair, and all gradient computation is ndarray-based, the entire pipeline runs on pure CPU with SIMD acceleration for inference forward passes.
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**Component-by-component GPU dependency analysis:**
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| Component | Source | GPU Dependency | SIMD-Only Mode |
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|-----------|--------|---------------|----------------|
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| `MicroLoRA.forward_simd()` | `lora/micro_lora.rs:279` | **None** — ARM NEON intrinsics with scalar fallback | NEON on aarch64, scalar on x86 |
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| `MicroLoRA.apply_gradients()` | `lora/micro_lora.rs:621+` | **None** — pure ndarray | Works everywhere |
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| `MicroLoRA.apply_gradients_with_ewc()` | `lora/micro_lora.rs:621+` | **None** — pure ndarray | Works everywhere |
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| `TrainingPipeline` | `lora/training.rs` | **None** — pure ndarray CPU | Works everywhere |
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| `EwcRegularizer` | `lora/training.rs` | **None** — pure ndarray CPU | Works everywhere |
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| `GrpoOptimizer` | `training/grpo.rs` | **None** — pure ndarray CPU | Works everywhere |
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| `ContrastiveTrainer` | `training/contrastive.rs:169-175` | **Optional** — `use_metal: true` default, but `Device::new_metal(0).unwrap_or(Device::Cpu)` fallback | Set `use_metal: false` for CPU-only; also has non-Candle pure CPU path (line 475) |
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| `MemoryDistiller` | `reasoning_bank/distillation.rs` | **None** — pure Rust | Works everywhere |
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| `PolicyStore` | `policy_store.rs` | **None** — pure Rust | Works everywhere |
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| **`RealContrastiveTrainer`** | `training/real_trainer.rs:178` | **Yes — Metal/Candle** | **NOT used in Phase 0.5** (used in full distillation only) |
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**Inference forward pass (for loss computation) SIMD support:**
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| Kernel | NEON (aarch64) | x86 | Source |
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|--------|---------------|-----|--------|
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| GEMM | `gemm_neon` | `gemm_scalar` fallback | `kernels/matmul.rs:520` |
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| GEMV | `gemv_neon` | `gemv_scalar` fallback | `kernels/matmul.rs:184` |
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| SiLU | `silu_neon_impl` (~3.5x speedup) | scalar fallback | `kernels/activations.rs` |
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| GeLU | `gelu_neon_impl` (~3.2x speedup) | scalar fallback | `kernels/activations.rs` |
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| ReLU | `relu_neon_impl` (~4.0x speedup) | scalar fallback | `kernels/activations.rs` |
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| RMSNorm | `rms_norm_neon` | scalar fallback | `kernels/norm.rs` |
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| RoPE | `apply_rope_neon` | scalar fallback | `kernels/rope.rs` |
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| Softmax | `softmax_neon` (~2.8x speedup) | scalar fallback | `kernels/activations.rs` |
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**Key observation**: The matmul kernels only dispatch on `target_arch = "aarch64"` vs scalar. There are **no explicit AVX2 or AVX512 SIMD implementations** for x86 in the current kernel codebase. This means:
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- **Apple Silicon (aarch64)**: Full NEON SIMD acceleration — primary target for SIMD-only mode
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- **x86 (AMD/Intel)**: Falls to scalar fallback — works but ~3-5x slower than NEON
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- **Future opportunity**: Adding AVX2/AVX512 kernels to `matmul.rs` would make x86 competitive with NEON
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**Throughput comparison for Phase 0.5 (100M tokens, ~200-400M trainable params, 3B active forward):**
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| Execution Mode | Forward tok/s | Effective Training tok/s | 100M Tokens | 500M Tokens |
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|---------------|--------------|------------------------|------------|------------|
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| Metal GPU (M4 Max) | ~500-1500 | ~300-700 | ~2-4 days | ~8-19 days |
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| **NEON SIMD only (M4 Max CPU)** | **~200-500** | **~100-300** | **~4-12 days** | **~19-58 days** |
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| **NEON SIMD only (M3 Ultra CPU)** | **~300-700** | **~150-400** | **~3-8 days** | **~14-39 days** |
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| x86 scalar (Ryzen 9, no AVX2 kernels) | ~50-150 | ~30-80 | ~14-39 days | ~72-193 days |
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**Why SIMD-only is ~2-3x slower than Metal (not 10x):**
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- Phase 0.5 training is dominated by the forward pass through the frozen 3B active parameters to compute loss against the teacher
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- The forward pass uses SIMD-accelerated GEMM/GEMV (`gemm_neon`/`gemv_neon`) which gets ~60-70% of Metal throughput for these matrix sizes
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- Gradient computation for the ~200-400M trainable params is pure ndarray — identical speed regardless of Metal availability
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- The training bottleneck is I/O (loading teacher activations from mmap) not compute, further narrowing the gap
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**Platform portability (bonus of SIMD-only mode):**
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SIMD-only mode extends Phase 0.5 beyond Mac Studio to any platform with ndarray support:
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| Platform | SIMD Path | Effective tok/s | Feasible? |
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|----------|----------|----------------|-----------|
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| Mac Studio M4 Max (aarch64) | NEON intrinsics | ~100-300 | **Yes — primary target** |
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| Mac Studio M3 Ultra (aarch64) | NEON intrinsics | ~150-400 | **Yes — faster than M4 Max** |
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| Linux ARM64 (Ampere/Graviton) | NEON intrinsics | ~80-200 | **Yes — cloud ARM instances** |
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| Linux x86 (Ryzen/Xeon) | Scalar fallback | ~30-80 | **Marginal — 100M tokens feasible (~14-39 days), 500M not practical** |
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| macOS Intel | Scalar fallback | ~20-50 | **Not recommended** |
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**Configuration for SIMD-only mode:**
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```rust
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// Phase 0.5 SIMD-only config (no Metal)
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let contrastive_config = ContrastiveConfig {
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use_metal: false, // Force CPU path in ContrastiveTrainer
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..Default::default()
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};
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// MicroLoRA — already pure SIMD/ndarray, no config change needed
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// TrainingPipeline — already pure ndarray
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// GrpoOptimizer — already pure ndarray
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// EwcRegularizer — already pure ndarray
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```
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The only config change is `ContrastiveTrainer.use_metal = false`. All other RLM components are GPU-agnostic by design.
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**SIMD-only Phase 0.5 exit criteria (in addition to standard Phase 0.5 criteria):**
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- [ ] All training completes without Metal GPU dependency
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- [ ] `ContrastiveTrainer` runs with `use_metal: false` and produces equivalent router accuracy
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- [ ] MicroLoRA `forward_simd()` executes NEON path on aarch64 (verified via `cfg` compile check)
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- [ ] Training throughput measured and documented for SIMD-only vs Metal comparison
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**Recommendation**: Use Metal when available (2-3x faster), fall back to SIMD-only when Metal is unavailable or on non-Mac platforms. The training code requires zero changes — only `ContrastiveTrainer.use_metal` needs to be set to `false`.
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**Reused**: 100% of existing RLM stack — `MicroLoRA` NEON forward, ndarray training, `ContrastiveTrainer` CPU fallback, all existing SIMD kernels.
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**New**: 0 lines. SIMD-only mode is already supported by the existing code paths; AD-20 documents this capability explicitly.
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---
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## Consequences
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@ -1177,6 +1274,8 @@ All three can be addressed by training only the FP16 components using the existi
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14. **Existing GGUF ecosystem**: Community-published GLM-4.7-Flash GGUFs (bartowski, unsloth) available as comparison baselines
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15. **Phase 0.5 RLM refinement at $0**: Existing MicroLoRA + GRPO + EWC++ + ContrastiveTrainer stack provides ~10-15 percentage point quality recovery over raw PTQ with zero new training code, running entirely on Mac Studio
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16. **100% RLM reuse for Phase 0.5**: No new training infrastructure needed — all 7 RLM components are production-tested and wire together directly
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17. **SIMD-only Phase 0.5**: Entire RLM refinement pipeline runs on pure CPU SIMD (NEON on aarch64) without Metal GPU — only ~2-3x slower than Metal, extends platform support to Linux ARM64 and (with scalar fallback) x86
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18. **Zero-config SIMD mode**: All training components (MicroLoRA, TrainingPipeline, EwcRegularizer, GrpoOptimizer) are already GPU-agnostic; only `ContrastiveTrainer.use_metal = false` needed for full SIMD-only execution
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### Negative
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@ -1187,6 +1286,7 @@ All three can be addressed by training only the FP16 components using the existi
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5. **Mixed-precision complexity**: Router (FP16) + experts (ternary) + attention (FP16/ternary) adds dispatch complexity
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6. **WASM limitation**: Ternary lookup table kernels may not translate efficiently to WASM SIMD
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7. **RLM scale gap**: Existing `RealContrastiveTrainer` targets 0.5B models (embedding_dim=896); scaling to 30B requires distributed data loading and increased batch sizes
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8. **No x86 SIMD kernels**: Current `kernels/matmul.rs` only implements NEON (aarch64); x86 falls to scalar fallback (~3-5x slower than NEON). Adding AVX2/AVX512 kernels would make x86 SIMD-only mode competitive but is not yet implemented
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### Risks
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@ -1284,3 +1384,6 @@ All three can be addressed by training only the FP16 components using the existi
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21. STBLLM: "Breaking the 1-bit Barrier" (ICLR 2025) — https://proceedings.iclr.cc/paper_files/paper/2025/file/ff997469ac66cf893c4183efeb22212a-Paper-Conference.pdf
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22. Apple Mac Studio Technical Specifications (2025) — https://www.apple.com/mac-studio/specs/
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23. RuvLLM Metal GEMV integration: `crates/ruvllm/src/kernels/matmul.rs:1444-1582`
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24. RuvLLM MicroLoRA NEON SIMD forward: `crates/ruvllm/src/lora/micro_lora.rs:279-390` (forward_simd, forward_simd_neon_impl)
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25. RuvLLM NEON SIMD kernels: `crates/ruvllm/src/kernels/` (matmul: gemm_neon/gemv_neon, activations: silu_neon/gelu_neon/relu_neon, norm: rms_norm_neon, rope: apply_rope_neon)
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26. RuvLLM ContrastiveTrainer CPU fallback: `crates/ruvllm/src/training/contrastive.rs:171-175` (Metal → CPU fallback) and `contrastive.rs:475` (non-Candle pure CPU path)
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@ -1,6 +1,6 @@
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# Domain-Driven Design: Craftsman Ultra 30b 1bit
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**Version:** 2.2
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**Version:** 2.3
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**Date:** 2026-02-03
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**Relates to:** ADR-017-craftsman-ultra-30b-1bit-bitnet-integration
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**Status:** Research / Pre-Implementation
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@ -84,6 +84,9 @@ The following terms have precise meaning within the Craftsman Ultra domain. All
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| **Frozen Ternary** | Expert FFN weights locked to their PTQ {-1,0,+1} values during Phase 0.5 refinement — not differentiable, not modified. |
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| **LoRA Correction** | Small FP16 additive output from MicroLoRA that compensates for ternary quantization error: `Y = BitLinear(X) + LoRA(X)`. |
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| **Router Repair** | Contrastive fine-tuning of FP16 router weights to correct misrouting caused by expert output distribution changes after PTQ. |
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| **SIMD-Only Mode** | Phase 0.5 execution mode where all training runs on pure CPU SIMD (NEON on aarch64) without Metal GPU. All RLM components are GPU-agnostic except ContrastiveTrainer which has an explicit CPU fallback path. ~2-3x slower than Metal but extends platform support beyond macOS. |
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| **NEON Intrinsics** | ARM SIMD instruction set used by MicroLoRA's `forward_simd_neon_impl()` for 8x-unrolled forward passes. Available on all Apple Silicon and ARM64 platforms. x86 platforms fall to scalar fallback. |
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| **Scalar Fallback** | Platform-agnostic non-SIMD code path used when NEON (aarch64) is unavailable. Provides identical results at ~3-5x lower throughput. Enables Phase 0.5 on x86 Linux/Windows. |
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---
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@ -548,7 +551,7 @@ The RLM Training Orchestration Context operates in a **lightweight refinement mo
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| `ContrastiveTrainer` | Router validation | **Router repair** |
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| `GrpoOptimizer` | Per-expert distillation reward | **Scale factor optimization reward** |
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| `EwcRegularizer` | Cross-expert stability | **Cross-step stability** |
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| Platform | Cloud GPU (4× A100) | **Mac Studio (Metal)** |
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| Platform | Cloud GPU (4× A100) | **Mac Studio (Metal or SIMD-only)** |
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| Cost | $1,300+ | **$0** |
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| New code | ~30% new | **~0% new** (only thin orchestrator) |
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@ -939,7 +942,7 @@ Assuming GLM-4.7-Flash architecture with ~3B active parameters per token:
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## 8.5 Training Infrastructure Model
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### Why Not Local CPU/SIMD
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### Why Not Local CPU/SIMD (for Phase 1+)
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The existing RuvLLM SIMD kernels (`crates/ruvllm/src/kernels/`) are **inference-only** — no backward pass, no gradient computation, no training support. The training code paths are:
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@ -947,7 +950,34 @@ The existing RuvLLM SIMD kernels (`crates/ruvllm/src/kernels/`) are **inference-
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- `EwcRegularizer` / LoRA training: Pure CPU via `ndarray` (no GPU acceleration)
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- SIMD kernels: Forward-pass optimizations only (flash attention, matmul, activations)
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At ~50-100 training tok/s on CPU, 200B tokens would require ~65 years. Not viable.
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At ~50-100 training tok/s on CPU, 200B tokens would require ~65 years. Not viable for Phase 1+.
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### Why SIMD-Only Works (for Phase 0.5)
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Phase 0.5 is fundamentally different from Phase 1+: it trains only ~200-400M FP16 parameters (1-2% of 30B) using existing RLM components that are already pure ndarray/CPU. The SIMD kernels are used for the forward pass through the frozen model to compute training loss, not for gradient computation.
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**GPU dependency analysis of Phase 0.5 components:**
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| Component | GPU Required? | SIMD Benefit |
|
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|-----------|--------------|-------------|
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| MicroLoRA forward pass | No — `forward_simd()` uses NEON intrinsics directly | ~3-4x over scalar |
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| MicroLoRA gradient computation | No — pure ndarray `apply_gradients()` | None (ndarray handles) |
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| TrainingPipeline | No — pure ndarray | None |
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| EwcRegularizer | No — pure ndarray | None |
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| GrpoOptimizer | No — pure ndarray | None |
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| ContrastiveTrainer | Optional — `use_metal: false` forces CPU | Candle CPU tensors |
|
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| Frozen model forward (loss computation) | No — SIMD inference kernels | NEON GEMM/GEMV ~3x |
|
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**Effective training throughput (SIMD-only, 100M-500M tokens):**
|
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|
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| Platform | SIMD | tok/s | 100M tokens | Feasible? |
|
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|----------|------|-------|-------------|-----------|
|
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| Mac Studio M4 Max | NEON | ~100-300 | 4-12 days | **Yes** |
|
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| Mac Studio M3 Ultra | NEON | ~150-400 | 3-8 days | **Yes** |
|
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| Linux ARM64 (Graviton3) | NEON | ~80-200 | 6-14 days | **Yes** |
|
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| Linux x86 (Ryzen 9) | Scalar | ~30-80 | 14-39 days | **Marginal** |
|
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|
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**Platform gap**: No AVX2/AVX512 SIMD kernels exist in `kernels/matmul.rs` — only `target_arch = "aarch64"` (NEON) vs scalar dispatch. x86 therefore falls to scalar, making it ~3-5x slower than NEON. Adding AVX2 kernels is an identified future improvement (see ADR-017 AD-20).
|
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|
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### Cloud GPU Distillation Strategy
|
||||
|
||||
|
|
@ -987,10 +1017,12 @@ Expert FFN (~1B params):
|
|||
|
||||
| Task | Location | Device | Duration |
|
||||
|------|----------|--------|----------|
|
||||
| **Phase 0.5 RLM refinement (Metal)** | **Mac Studio** | **Metal GPU + CPU ndarray** | **3-14 days** |
|
||||
| **Phase 0.5 RLM refinement (SIMD-only)** | **Mac Studio or Linux ARM64** | **NEON SIMD + CPU ndarray** | **4-24 days** |
|
||||
| Expert distillation (Phase 1) | GCP 4×A100 spot | CUDA | ~46 days |
|
||||
| Router contrastive validation | GCP 1×A100 or local Mac | CUDA/Metal | Hours |
|
||||
| Router contrastive validation | GCP 1×A100 or local Mac | CUDA/Metal/CPU | Hours |
|
||||
| Inference benchmark (TL1/TL2) | Local workstation | CPU SIMD (AVX2/NEON) | Minutes |
|
||||
| MicroLoRA adaptation | Local / edge | CPU (ndarray) | <1ms/update |
|
||||
| MicroLoRA adaptation | Local / edge | CPU (ndarray + NEON SIMD) | <1ms/update |
|
||||
| GGUF export | Local | CPU | Minutes |
|
||||
| Kernel correctness tests | Local | CPU SIMD | Seconds |
|
||||
|
||||
|
|
@ -1089,6 +1121,9 @@ All changes are additive. No existing backend, model, or API is modified. The `B
|
|||
| 15 | Optimal MicroLoRA rank for Phase 0.5? | Quality vs speed | Open | Rank-1 is faster, rank-2 is 5% faster due to SIMD but has 2× params. Empirical testing needed. |
|
||||
| 16 | LoRA adapter persistence in GGUF? | Export format | Open | Store LoRA A/B matrices as separate tensors in GGUF, or merge into ternary+FP16 hybrid format? |
|
||||
| 17 | Phase 0.5 LoRA → Phase 1 distillation init? | Continuity | Open | Can Phase 0.5 LoRA corrections inform Phase 1 shadow weight initialization for faster convergence? |
|
||||
| 18 | Add AVX2/AVX512 SIMD kernels to `matmul.rs`? | x86 SIMD-only performance | Open | Current kernels only have NEON (aarch64) + scalar fallback. Adding AVX2 would make x86 SIMD-only Phase 0.5 ~3-5x faster. Is it worth the effort vs just using ARM? |
|
||||
| 19 | SIMD-only vs Metal quality equivalence? | Phase 0.5 validation | Open | Does ContrastiveTrainer produce identical router accuracy on CPU vs Metal? Need empirical comparison to confirm no numerical divergence. |
|
||||
| 20 | Cloud ARM64 instances for SIMD-only Phase 0.5? | Platform portability | Open | AWS Graviton3/4 or Ampere Altra instances with 128+ GB RAM could run SIMD-only Phase 0.5 without Mac Studio. Cost-competitive? |
|
||||
|
||||
---
|
||||
|
||||
|
|
@ -1111,3 +1146,6 @@ All changes are additive. No existing backend, model, or API is modified. The `B
|
|||
- BitDistill: "BitNet Distillation" (arXiv:2510.13998, Oct 2025)
|
||||
- bartowski, GLM-4.7-Flash-GGUF quantizations: https://huggingface.co/bartowski/zai-org_GLM-4.7-Flash-GGUF
|
||||
- llama.cpp IQ1_S blind testing: https://github.com/ggml-org/llama.cpp/discussions/5962
|
||||
- RuvLLM MicroLoRA NEON SIMD: `crates/ruvllm/src/lora/micro_lora.rs:279-390`
|
||||
- RuvLLM NEON SIMD kernels: `crates/ruvllm/src/kernels/` (gemm_neon, gemv_neon, silu_neon, gelu_neon, relu_neon, rms_norm_neon, apply_rope_neon)
|
||||
- RuvLLM ContrastiveTrainer CPU fallback: `crates/ruvllm/src/training/contrastive.rs:171-175`
|
||||
|
|
|
|||
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