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Zhang Jingqiang Working 0b67587d83
increase MSRV to 1.70 (#72) 
* increase MSRV to 1.70

* g3bench: use IsTerminal in stdlib

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Co-authored-by: Zhang Jingqiang <zh_jq@outlook.com>
2023-06-02 10:28:24 +08:00
..
src increase MSRV to 1.70 (#72) 2023-06-02 10:28:24 +08:00
Cargo.toml increase MSRV to 1.70 (#72) 2023-06-02 10:28:24 +08:00