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10 commits

Author SHA1 Message Date
Zhang Jingqiang Working
0b67587d83
increase MSRV to 1.70 (#72) 
* increase MSRV to 1.70

* g3bench: use IsTerminal in stdlib

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Co-authored-by: Zhang Jingqiang <zh_jq@outlook.com>
 2023-06-02 10:28:24 +08:00
Zhang Jingqiang
a2256ac8c1 update doc 2023-05-30 14:01:02 +08:00
Zhang Jingqiang
1fac2f45b3 update doc 2023-05-27 09:09:14 +08:00
Zhang Jingqiang
75e50020b9 update doc 2023-05-15 16:07:02 +08:00
Zhang Jingqiang
99f8706785 update doc 2023-05-04 17:52:52 +08:00
Zhang
250abcbd35 update doc 2023-04-13 11:10:15 +08:00
zhangjingqiang
075de618ba add zh_CN README 2023-04-12 11:08:15 +08:00
zhangjingqiang
5c569fc387 fix typo 2023-04-10 16:35:24 +08:00
zhangjingqiang
515670c4dd rename g3rcgen to g3fcgen 2023-04-04 11:03:05 +08:00
zhangjingqiang
13716f4923 initial commit 2023-03-09 17:55:45 +08:00