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https://github.com/HyperDbg/HyperDbg.git
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Fix build issues of the Intel PT in hypertrace
This commit is contained in:
sina
parent
5b8076510a
commit
0cd11e136b
7 changed files with 73 additions and 84 deletions
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@ -62,6 +62,7 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "headers", "headers", "{D67D
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include\SDK\Headers\Ioctls.h = include\SDK\Headers\Ioctls.h
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include\SDK\headers\LbrDefinitions.h = include\SDK\headers\LbrDefinitions.h
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include\SDK\headers\Pcie.h = include\SDK\headers\Pcie.h
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include\SDK\headers\PtDefinitions.h = include\SDK\headers\PtDefinitions.h
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include\SDK\Headers\RequestStructures.h = include\SDK\Headers\RequestStructures.h
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include\SDK\Headers\ScriptEngineCommonDefinitions.h = include\SDK\Headers\ScriptEngineCommonDefinitions.h
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include\SDK\Headers\Symbols.h = include\SDK\Headers\Symbols.h
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@ -40,7 +40,7 @@ extern VOID inline AsmRestoreToVmxOffState();
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extern NTSTATUS inline AsmVmxVmcall(UINT64 VmcallNumber,
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UINT64 OptionalParam1,
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UINT64 OptionalParam2,
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INT64 OptionalParam3);
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UINT64 OptionalParam3);
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/**
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* @brief Hyper-v vmcall handler
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@ -405,7 +405,7 @@ HyperTracePtFlush(HYPERTRACE_PT_OPERATION_PACKETS * HyperTraceOperationRequest)
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BOOLEAN
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HyperTracePtFilter(HYPERTRACE_PT_OPERATION_PACKETS * Req)
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{
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PT_FILTER_OPTIONS FilterOptions = {0};
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PT_FILTER_OPTIONS FilterOptions = {0};
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BOOLEAN WasEnabled = g_ProcessorTraceEnabled;
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BOOLEAN BufferChanged = FALSE;
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UINT64 ExistingSize = 0;
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@ -109,12 +109,12 @@ PtVaToPa(PVOID Va)
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* @return INT32 0 on success, -1 on failure (outputs untouched).
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*/
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static INT32
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PtMmapCpuRegionToUser(PVOID MainVa,
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UINT64 MainPhysical,
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SIZE_T MainSize,
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UINT64 OverflowPhysical,
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SIZE_T OverflowSize,
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PMDL * OutMdl,
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PtMmapCpuRegionToUser(PVOID MainVa,
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UINT64 MainPhysical,
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SIZE_T MainSize,
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UINT64 OverflowPhysical,
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SIZE_T OverflowSize,
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PMDL * OutMdl,
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PVOID * OutUserVa)
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{
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SIZE_T TotalSize = MainSize + OverflowSize;
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@ -1429,8 +1429,8 @@ PtFilter(const PT_FILTER_OPTIONS * FilterOptions)
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//
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// Apply only the user-tunable fields to this CPU's per-CPU config.
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//
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Cpu->Config.TraceUser = FilterOptions->TraceUser;
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Cpu->Config.TraceKernel = FilterOptions->TraceKernel;
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Cpu->Config.TraceUser = FilterOptions->TraceUser;
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Cpu->Config.TraceKernel = FilterOptions->TraceKernel;
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if (FilterOptions->TargetCr3 != 0 && !Caps.Cr3Filtering)
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{
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@ -67,6 +67,14 @@
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#include "platform/kernel/header/PlatformIo.h"
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#include "platform/kernel/header/PlatformEvent.h"
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//
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// Definition of tracing types and structures (Processor Trace).
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// Pt.h must come before broadcast/Broadcast.h because Broadcast.h
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// references PT_FILTER_OPTIONS in its function signatures.
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//
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#include "pt/Pt.h"
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#include "api/PtApi.h"
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//
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// DPC and broadcasting function headers
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//
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@ -105,26 +113,6 @@
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#include "lbr/Lbr.h"
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#include "api/LbrApi.h"
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//
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// Definition of tracing types and structures (Processor Trace).
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// Pt.h must come before broadcast/Broadcast.h because Broadcast.h
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// references PT_FILTER_OPTIONS in its function signatures.
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//
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#include "pt/Pt.h"
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#include "api/PtApi.h"
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//
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// DPC and broadcasting function headers
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//
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#include "broadcast/Dpc.h"
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#include "broadcast/DpcRoutines.h"
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#include "broadcast/Broadcast.h"
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//
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// Unload function (to be called when the driver is unloaded)
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//
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#include "common/UnloadDll.h"
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//
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// Export functions
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//
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@ -91,30 +91,30 @@ typedef union _PT_RTIT_CTL_REGISTER
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{
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struct
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{
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UINT64 TraceEn : 1; /* [0] Enable tracing */
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UINT64 CycEn : 1; /* [1] CYC packets */
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UINT64 Os : 1; /* [2] Trace CPL 0 */
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UINT64 User : 1; /* [3] Trace CPL > 0 */
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UINT64 PwrEvtEn : 1; /* [4] Power event trace */
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UINT64 FupOnPtw : 1; /* [5] FUP on PTWRITE */
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UINT64 FabricEn : 1; /* [6] Trace to fabric (must be 0) */
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UINT64 TraceEn : 1; /* [0] Enable tracing */
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UINT64 CycEn : 1; /* [1] CYC packets */
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UINT64 Os : 1; /* [2] Trace CPL 0 */
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UINT64 User : 1; /* [3] Trace CPL > 0 */
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UINT64 PwrEvtEn : 1; /* [4] Power event trace */
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UINT64 FupOnPtw : 1; /* [5] FUP on PTWRITE */
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UINT64 FabricEn : 1; /* [6] Trace to fabric (must be 0) */
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UINT64 Cr3Filter : 1; /* [7] Filter by CR3 */
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UINT64 ToPA : 1; /* [8] Use ToPA output scheme */
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UINT64 MtcEn : 1; /* [9] MTC packets */
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UINT64 TscEn : 1; /* [10] TSC packets */
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UINT64 DisRetc : 1; /* [11] Disable RET compression */
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UINT64 PtwEn : 1; /* [12] PTWRITE packets */
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UINT64 BranchEn : 1; /* [13] Branch trace (TNT, TIP, FUP) */
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UINT64 MtcFreq : 4; /* [14:17] MTC frequency */
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UINT64 ToPA : 1; /* [8] Use ToPA output scheme */
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UINT64 MtcEn : 1; /* [9] MTC packets */
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UINT64 TscEn : 1; /* [10] TSC packets */
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UINT64 DisRetc : 1; /* [11] Disable RET compression */
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UINT64 PtwEn : 1; /* [12] PTWRITE packets */
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UINT64 BranchEn : 1; /* [13] Branch trace (TNT, TIP, FUP) */
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UINT64 MtcFreq : 4; /* [14:17] MTC frequency */
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UINT64 Reserved0 : 1; /* [18] Must be 0 */
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UINT64 CycThresh : 4; /* [19:22] CYC threshold */
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UINT64 Reserved1 : 1; /* [23] Must be 0 */
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UINT64 PsbFreq : 4; /* [24:27] PSB frequency */
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UINT64 PsbFreq : 4; /* [24:27] PSB frequency */
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UINT64 Reserved2 : 4; /* [28:31] Must be 0 */
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UINT64 Addr0Cfg : 4; /* [32:35] Range 0 mode (1=filter / 2=stop) */
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UINT64 Addr1Cfg : 4; /* [36:39] Range 1 mode */
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UINT64 Addr2Cfg : 4; /* [40:43] Range 2 mode */
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UINT64 Addr3Cfg : 4; /* [44:47] Range 3 mode */
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UINT64 Addr0Cfg : 4; /* [32:35] Range 0 mode (1=filter / 2=stop) */
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UINT64 Addr1Cfg : 4; /* [36:39] Range 1 mode */
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UINT64 Addr2Cfg : 4; /* [40:43] Range 2 mode */
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UINT64 Addr3Cfg : 4; /* [44:47] Range 3 mode */
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UINT64 Reserved3 : 16; /* [48:63] Must be 0 */
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};
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UINT64 Value;
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@ -128,17 +128,17 @@ typedef union _PT_RTIT_STATUS_REGISTER
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{
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struct
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{
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UINT64 FilterEn : 1; /* [0] RO: IP filter allowing trace */
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UINT64 ContextEn : 1; /* [1] RO: Context (CR3) allowing trace */
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UINT64 TriggerEn : 1; /* [2] RO: Trigger conditions met */
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UINT64 Reserved0 : 1; /* [3] Must be 0 */
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UINT64 Error : 1; /* [4] RO/Sticky: Operational error */
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UINT64 Stopped : 1; /* [5] RO: TraceStop hit */
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UINT64 PendTopaPmi : 1; /* [6] RW: ToPA PMI pending — clear this */
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UINT64 PendPsbPmi : 1; /* [7] RW: PSB+ PMI pending — clear this */
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UINT64 Reserved1 : 24; /* [8:31] Must be 0 */
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UINT64 FilterEn : 1; /* [0] RO: IP filter allowing trace */
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UINT64 ContextEn : 1; /* [1] RO: Context (CR3) allowing trace */
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UINT64 TriggerEn : 1; /* [2] RO: Trigger conditions met */
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UINT64 Reserved0 : 1; /* [3] Must be 0 */
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UINT64 Error : 1; /* [4] RO/Sticky: Operational error */
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UINT64 Stopped : 1; /* [5] RO: TraceStop hit */
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UINT64 PendTopaPmi : 1; /* [6] RW: ToPA PMI pending — clear this */
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UINT64 PendPsbPmi : 1; /* [7] RW: PSB+ PMI pending — clear this */
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UINT64 Reserved1 : 24; /* [8:31] Must be 0 */
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UINT64 PacketByteCnt : 17; /* [32:48] Bytes since last PSB */
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UINT64 Reserved2 : 15; /* [49:63] Must be 0 */
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UINT64 Reserved2 : 15; /* [49:63] Must be 0 */
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};
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UINT64 Value;
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} PT_RTIT_STATUS_REGISTER, *PPT_RTIT_STATUS_REGISTER;
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@ -151,9 +151,9 @@ typedef union _PT_OUTPUT_MASK_PTRS_REGISTER
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{
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struct
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{
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UINT64 LowerMask : 7; /* [0:6] Forced to 0x7F */
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UINT64 LowerMask : 7; /* [0:6] Forced to 0x7F */
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UINT64 MaskOrTableOffset : 25; /* [7:31] ToPA: table entry index */
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UINT64 OutputOffset : 32; /* [32:63] Byte offset in current entry */
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UINT64 OutputOffset : 32; /* [32:63] Byte offset in current entry */
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};
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UINT64 Value;
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} PT_OUTPUT_MASK_PTRS_REGISTER, *PPT_OUTPUT_MASK_PTRS_REGISTER;
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@ -166,15 +166,15 @@ typedef union _PT_TOPA_ENTRY
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{
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struct
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{
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UINT64 End : 1; /* [0] Last entry — wraps to next table */
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UINT64 End : 1; /* [0] Last entry — wraps to next table */
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UINT64 Reserved0 : 1; /* [1] Must be 0 */
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UINT64 Int : 1; /* [2] Generate PMI when region fills */
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UINT64 Int : 1; /* [2] Generate PMI when region fills */
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UINT64 Reserved1 : 1; /* [3] Must be 0 */
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UINT64 Stop : 1; /* [4] Stop tracing when region fills */
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UINT64 Stop : 1; /* [4] Stop tracing when region fills */
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UINT64 Reserved2 : 1; /* [5] Must be 0 */
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UINT64 Size : 4; /* [6:9] Region size (4K*2^N) */
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UINT64 Size : 4; /* [6:9] Region size (4K*2^N) */
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UINT64 Reserved3 : 2; /* [10:11] Must be 0 */
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UINT64 BaseAddr : 36; /* [12:47] Physical address >> 12 */
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UINT64 BaseAddr : 36; /* [12:47] Physical address >> 12 */
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UINT64 Reserved4 : 16; /* [48:63] Must be 0 */
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};
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UINT64 Value;
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@ -189,24 +189,24 @@ typedef union _PT_TOPA_ENTRY
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*/
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typedef struct _PT_CAPABILITIES
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{
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UINT32 Cr3Filtering : 1; /* Can filter by process CR3 */
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UINT32 Cr3Filtering : 1; /* Can filter by process CR3 */
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UINT32 PsbCycConfigurable : 1; /* PSBFreq and CYC configurable */
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UINT32 IpFiltering : 1; /* IP filtering and TraceStop supported */
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UINT32 MtcSupport : 1; /* MTC packets supported */
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UINT32 PtwriteSupport : 1; /* PTWRITE instruction supported */
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UINT32 PowerEventTrace : 1; /* Power event trace supported */
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UINT32 VmxSupport : 1; /* PT works in VMX operations */
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UINT32 TopaOutput : 1; /* ToPA output scheme supported */
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UINT32 TopaMultiEntry : 1; /* ToPA tables can have >1 entry */
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UINT32 SingleRangeOutput : 1; /* Single contiguous range output */
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UINT32 TransportOutput : 1; /* Trace transport subsystem output */
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UINT32 IpPayloadsAreLip : 1; /* IP payloads are LIP (not RIP) */
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UINT32 Reserved : 20;
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UINT32 IpFiltering : 1; /* IP filtering and TraceStop supported */
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UINT32 MtcSupport : 1; /* MTC packets supported */
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UINT32 PtwriteSupport : 1; /* PTWRITE instruction supported */
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UINT32 PowerEventTrace : 1; /* Power event trace supported */
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UINT32 VmxSupport : 1; /* PT works in VMX operations */
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UINT32 TopaOutput : 1; /* ToPA output scheme supported */
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UINT32 TopaMultiEntry : 1; /* ToPA tables can have >1 entry */
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UINT32 SingleRangeOutput : 1; /* Single contiguous range output */
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UINT32 TransportOutput : 1; /* Trace transport subsystem output */
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UINT32 IpPayloadsAreLip : 1; /* IP payloads are LIP (not RIP) */
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UINT32 Reserved : 20;
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UINT32 NumAddrRanges; /* Number of ADDRn_CFG pairs (0-4) */
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UINT16 MtcPeriodBitmap; /* Supported MTC period values */
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UINT16 CycThresholdBitmap; /* Supported CYC threshold values */
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UINT16 PsbFreqBitmap; /* Supported PSB frequency values */
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UINT32 NumAddrRanges; /* Number of ADDRn_CFG pairs (0-4) */
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UINT16 MtcPeriodBitmap; /* Supported MTC period values */
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UINT16 CycThresholdBitmap; /* Supported CYC threshold values */
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UINT16 PsbFreqBitmap; /* Supported PSB frequency values */
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} PT_CAPABILITIES, *PPT_CAPABILITIES;
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@ -1394,8 +1394,8 @@ typedef struct _HYPERTRACE_PT_OPERATION_PACKETS
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//
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// SIZE output: per-CPU bytes-written snapshot
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//
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UINT32 NumCpus; /* CPUs populated in BytesPerCpu */
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UINT32 Reserved2; /* Padding to 8-align the array */
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UINT32 NumCpus; /* CPUs populated in BytesPerCpu */
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UINT32 Reserved2; /* Padding to 8-align the array */
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UINT64 BytesPerCpu[PT_MAX_CPUS_FOR_MMAP];
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} HYPERTRACE_PT_OPERATION_PACKETS, *PHYPERTRACE_PT_OPERATION_PACKETS;
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