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New version, new tarball. This is an attempt at a fix for issue #129
Because I don't want to break existing cpu logic, I just added in a rizen switch, which will just use cpu_core_count value, then trigger HT output. This fix may or may not work, but the issue poster vanished and has not followed up. For now I'm keeping this a Ryzen specific adjustment, but it may be safe to extend it further, that is, if siblings > 1 && siblings = 2 * cores then it's HT.
This commit is contained in:
parent
97187fa32e
commit
3b46a486af
35
inxi
35
inxi
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@ -2,8 +2,8 @@
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########################################################################
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########################################################################
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SELF_NAME='inxi'
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SELF_NAME='inxi'
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# don't quote the following, parsers grab these too
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# don't quote the following, parsers grab these too
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SELF_VERSION=2.3.50
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SELF_VERSION=2.3.51
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SELF_DATE=2017-11-28
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SELF_DATE=2017-11-31
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SELF_PATCH=00
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SELF_PATCH=00
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########################################################################
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########################################################################
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#### SPECIAL THANKS
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#### SPECIAL THANKS
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@ -4953,13 +4953,7 @@ get_cpu_core_count_alpha()
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2) CPU_COUNT_ALPHA='Dual';;
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2) CPU_COUNT_ALPHA='Dual';;
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3) CPU_COUNT_ALPHA='Triple';;
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3) CPU_COUNT_ALPHA='Triple';;
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4) CPU_COUNT_ALPHA='Quad';;
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4) CPU_COUNT_ALPHA='Quad';;
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5) CPU_COUNT_ALPHA='Penta';;
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*) CPU_COUNT_ALPHA=$1;;
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6) CPU_COUNT_ALPHA='Hexa';;
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7) CPU_COUNT_ALPHA='Hepta';;
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8) CPU_COUNT_ALPHA='Octa';;
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9) CPU_COUNT_ALPHA='Ennea';;
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10) CPU_COUNT_ALPHA='Deca';;
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*) CPU_COUNT_ALPHA='Multi';;
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esac
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esac
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log_function_data "CPU_COUNT_ALPHA: $CPU_COUNT_ALPHA"
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log_function_data "CPU_COUNT_ALPHA: $CPU_COUNT_ALPHA"
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@ -5393,6 +5387,7 @@ get_cpu_ht_multicore_smp_data()
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arm_count = 0
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arm_count = 0
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nr = 0
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nr = 0
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bArm = "false"
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bArm = "false"
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bRizen = "false"
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bProcInt = "false" # this will avoid certain double counts with processor/Processor lines
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bProcInt = "false" # this will avoid certain double counts with processor/Processor lines
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bXeon = "false"
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bXeon = "false"
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}
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}
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@ -5400,8 +5395,12 @@ get_cpu_ht_multicore_smp_data()
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/^model name/ && ( $0 ~ /Xeon/ ) {
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/^model name/ && ( $0 ~ /Xeon/ ) {
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bXeon = "true"
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bXeon = "true"
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}
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}
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# amd rizen 16/32 core maybe
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/^cpu_family/ && ($2 == 23) {
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bRizen = "true"
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}
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# only do this once since sibling count does not change.
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# only do this once since sibling count does not change.
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/^siblings/ && ( bXeon == "true" ) && ( siblings == 0 ) {
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/^siblings/ && ( bXeon == "true" || bRizen == "true" ) && ( siblings == 0 ) {
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gsub(/[^0-9]/,"",$NF)
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gsub(/[^0-9]/,"",$NF)
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if ( $NF != "" ) {
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if ( $NF != "" ) {
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siblings = $NF
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siblings = $NF
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@ -5444,6 +5443,8 @@ get_cpu_ht_multicore_smp_data()
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}
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}
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# array of core ids, again, here we may have HT, so we need to create an array of the
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# array of core ids, again, here we may have HT, so we need to create an array of the
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# actual core ids. As With physical, we cannot assume this will be here in a vm
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# actual core ids. As With physical, we cannot assume this will be here in a vm
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# also, for xeon/rizen, this can be misleading because there may be two cpus
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# inside the single cpu body, which leads to: 0-7 then 0-7 for a rizen 16 core ht
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/^core id/ {
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/^core id/ {
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core_iter = $NF
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core_iter = $NF
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a_core_id[core_iter] = $NF
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a_core_id[core_iter] = $NF
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@ -5471,7 +5472,8 @@ get_cpu_ht_multicore_smp_data()
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num_of_physical_cpus++
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num_of_physical_cpus++
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}
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}
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i = 0
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i = 0
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## count unique cores ##
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## count unique cores. Fails for 16 core rizen, which appears to be
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## using 2x8 core internally, core id 0-7 repeats 2 times.
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for ( i in a_core_id ) {
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for ( i in a_core_id ) {
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num_of_cores++
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num_of_cores++
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}
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}
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@ -5480,6 +5482,10 @@ get_cpu_ht_multicore_smp_data()
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if ( bXeon == "true" && num_of_cores == 1 && siblings > 1 ) {
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if ( bXeon == "true" && num_of_cores == 1 && siblings > 1 ) {
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num_of_cores = siblings/2
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num_of_cores = siblings/2
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}
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}
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#
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if ( bRizen == "true"){
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num_of_cores = cpu_core_count
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}
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# final check, override the num of cores value if it clearly is wrong
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# final check, override the num of cores value if it clearly is wrong
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# and use the raw core count and synthesize the total instead of real count
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# and use the raw core count and synthesize the total instead of real count
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if ( ( num_of_cores == 0 ) && ( cpu_core_count * num_of_physical_cpus > 1 ) ) {
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if ( ( num_of_cores == 0 ) && ( cpu_core_count * num_of_physical_cpus > 1 ) ) {
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@ -5501,6 +5507,7 @@ get_cpu_ht_multicore_smp_data()
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####################################################################
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####################################################################
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# algorithm
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# algorithm
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# if > 1 processor && processor id (physical id) == core id then Hyperthreaded (HT)
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# if > 1 processor && processor id (physical id) == core id then Hyperthreaded (HT)
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# if siblings > 1 && siblings == 2 * num_of_cores (cpu_core_count) then Hyperthreaded (HT)
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# if > 1 processor && processor id (physical id) != core id then Multi-Core Processors (MCP)
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# if > 1 processor && processor id (physical id) != core id then Multi-Core Processors (MCP)
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# if > 1 processor && processor ids (physical id) > 1 then Multiple Processors (SMP)
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# if > 1 processor && processor ids (physical id) > 1 then Multiple Processors (SMP)
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# if = 1 processor then single core/processor Uni-Processor (UP)
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# if = 1 processor then single core/processor Uni-Processor (UP)
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@ -5512,6 +5519,9 @@ get_cpu_ht_multicore_smp_data()
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else if ( bXeon == "true" && siblings > 1 ) {
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else if ( bXeon == "true" && siblings > 1 ) {
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cpu_type = cpu_type "HT-"
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cpu_type = cpu_type "HT-"
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}
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}
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else if ( siblings > 1 && siblings == 2 * num_of_cores ){
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cpu_type = cpu_type "HT-"
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}
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# non-HT multi-core or HT multi-core
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# non-HT multi-core or HT multi-core
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if (( num_of_processors == num_of_cores) || ( num_of_physical_cpus < num_of_cores)) {
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if (( num_of_processors == num_of_cores) || ( num_of_physical_cpus < num_of_cores)) {
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cpu_type = cpu_type "MCP-"
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cpu_type = cpu_type "MCP-"
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@ -13295,7 +13305,8 @@ print_cpu_data()
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if [[ -n ${a_cpu_working[2]} ]];then
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if [[ -n ${a_cpu_working[2]} ]];then
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if [[ -z $BSD_TYPE ]];then
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if [[ -z $BSD_TYPE ]];then
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# AMD SOS chips appear to report full L2 cache per core
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# AMD SOS chips appear to report full L2 cache per core
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if [[ "${a_cpu_info[3]}" == 'amd' ]] && [[ "${a_cpu_info[4]}" == '14' || "${a_cpu_info[4]}" == '16' ]];then
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if [[ "${a_cpu_info[3]}" == 'amd' ]] &&
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[[ "${a_cpu_info[4]}" == '14' || "${a_cpu_info[4]}" == '16' ]];then
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cpu_cache=$( calculate_multicore_data "${a_cpu_working[2]}" "$cpu_physical_count" )
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cpu_cache=$( calculate_multicore_data "${a_cpu_working[2]}" "$cpu_physical_count" )
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elif [[ $cpu_vendor != 'intel' ]];then
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elif [[ $cpu_vendor != 'intel' ]];then
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cpu_cache=$( calculate_multicore_data "${a_cpu_working[2]}" "$(( $cpu_core_count * $cpu_physical_count ))" )
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cpu_cache=$( calculate_multicore_data "${a_cpu_working[2]}" "$(( $cpu_core_count * $cpu_physical_count ))" )
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@ -1,3 +1,24 @@
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=====================================================================================
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Version: 2.3.51
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Patch Version: 00
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Script Date: 2017-11-31
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-----------------------------------
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Changes:
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-----------------------------------
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New version, new tarball. This is an attempt at a fix for issue #129
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Because I don't want to break existing cpu logic, I just added in a rizen switch,
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which will just use cpu_core_count value, then trigger HT output.
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This fix may or may not work, but the issue poster vanished and has not followed up.
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For now I'm keeping this a Ryzen specific adjustment, but it may be safe to extend
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it further, that is, if siblings > 1 && siblings = 2 * cores then it's HT.
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-----------------------------------
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-- Harald Hope - Fri, 01 Dec 2017 13:21:13 -0800
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=====================================================================================
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=====================================================================================
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Version: 2.3.50
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Version: 2.3.50
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Patch Version: 00
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Patch Version: 00
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